Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method

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Permanent URL	http://hdl.lib.byu.edu/1877/2361
Title	Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method
BYU Creator	Mercer, Eric G.
Creator	Kitai, Tomoya Myers, Chris Oguro, Yusuke Yoneda, Tomohiro
Keywords	level-oriented model; timed asynchronous circuits; formal verification; time Petri nets
Description/Abstract	Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits. On the other hand, in order to use such a model on large circuits, techniques to avoid the state explosion problem must be developed. This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the correctness of the verification.
Source	T. Kitai, Y. Oguro, T. Yoneda, E. G. Mercer, and C. J. Myers, "Level-oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method" in Proceedings of Pacific Rim International Symposium on Dependable Computing, pages 210-220, 2002.;
Publisher	IEEE
Date Original	2002
Date Digital	2010-08-17
Language	English eng en
Publication Type	Articles Conference Proceedings
Type	Text
Format	application/pdf
Owning Institution	Brigham Young University
BYU College	College of Physical and Mathematical Sciences
BYU Department	Computer Science
Copyright Status	(c) 2002 Institute of Electrical and Electronics Engineers;
Copyright Use Information	http://www.lib.byu.edu/generic_copyright.html

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Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method

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