Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets

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Permanent URL	http://hdl.lib.byu.edu/1877/43
Title	Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets
BYU Creator	Graham, Paul S. Rollins, Nathaniel Wirthlin, Michael J.
Creator	Caffrey, Michael P.
Keywords	FPGA Reliability; I/O
Description/Abstract	Sponsorship: Los Alamos National Laboratories (LA-UR-02-3163). Field programmable gate arrays (FPGAs) are an attractive alternative for space-based remote sensing applications. However, SRAM-based FPGAs are sensitive to radiation induced single-event upsets within the configuration memory. Such configuration upsets may change the logic, routing, and operating modes of a user FPGA design. Upsets within the configuration of an I/O block are especially troublesome as they may impact the operation of other system components. This paper will evaluate the operation of the I/O block within the Xilinx Virtex FPGA in the presence of configuration memory upsets and introduce techniques for detecting and repairing such failures.
Source	Nathan Rollins, Michael J. Wirthlin, Michael Caffrey, and Paul Graham, "Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets", 5th Annual International Conference on Military and Aerospace Programmable Logic Devices (MAPLD), Paper C3, September 2002;
Publisher	NASA Office of Logic Design
Date Original	2002
Date Digital	2004-09-15
Language	English eng en
Publication Type	Peer-Reviewed Articles
Type	Text
Format	application/pdf
Owning Institution	Brigham Young University
BYU College	Ira A. Fulton College of Engineering and Technology
BYU Department	Electrical and Computer Engineering
Copyright Status	(c) 2002 Los Alamos National Laboratory;
Copyright Use Information	http://www.lib.byu.edu/generic_copyright.html

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Reliability of Programmable Input/Output Pins in the Presence of Configuration Upsets

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