Evaluating TMR Techniques in the Presence of Single Event Upsets

View Description

Download

small (250x250 max)

medium (500x500 max)

large ( > 500x500)

Full Resolution

you wish to report:

Your comment:

Your Name:

Submit

Cancel

...

Rating
Permanent URL	http://hdl.lib.byu.edu/1877/44
Title	Evaluating TMR Techniques in the Presence of Single Event Upsets
BYU Creator	Graham, Paul S. Rollins, Nathaniel Wirthlin, Michael J.
Creator	Caffrey, Michael P.
Keywords	FPGA Reliability; TMR
Description/Abstract	Sponsorship: Los Alamos National Labs (LA-UR-03-7525). Field programmable gate arrays (FPGAs) are sensitive to radiation-induced single event upsets (SEUs) within the configuration memory. Triple modular redundancy (TMR) is a technique commonly used to mitigate against design failures caused by SEUs. This paper evaluates the effectiveness and cost of TMR on two different counter designs in the presence of SEUs. The evaluation measures the reliability, area cost, and speed of different TMR styles. The tests show that when feedback TMR is used with triplicated clocks, it is possible to have counter design which is insensitive to any single configuration upset.
Source	13;
Publisher	NASA Office of Logic Design
Date Original	2003
Date Digital	2004-09-15
Language	English eng en
Publication Type	Peer-Reviewed Articles
Type	Text
Format	application/pdf
Owning Institution	Brigham Young University
BYU College	Ira A. Fulton College of Engineering and Technology
BYU Department	Electrical and Computer Engineering
Copyright Status	(c) 2003 Los Alamos National Laboratory;
Copyright Use Information	http://www.lib.byu.edu/generic_copyright.html

Find results with: